Enabling 1588v2 on a Specific Interface

This section describes how to enable 1588v2 on a specific interface. 1588v2 takes effect after you configure 1588v2 in the system and interface views. You can set 1588v2 parameters in the interface view. The parameters include the link delay measurement mechanism, asymmetric delay correction, and timestamping mode.

Context

Two devices exchange Announce packets to determine the master/slave relationship. The master device sends Sync packets to notify the slave device of time signal parameters and uses a delay measurement mechanism to achieve time signals accuracy.

After 1588v2 is enabled and a device type is specified on a specific 1588v2 router, enable 1588v2 and configure 1588v2 functions on each interface:
  • Delay measurement mechanisms for the OC, BC, and TCandBC

    Different delays on links deteriorate the accuracy of 1588v2 time synchronization. 1588v2 uses the delay measurement mechanism to correct time signals. A delay measurement process is implemented by sending delay measurement request packets and delay response packets. Either of the following parameters can be configured in the ptp delay-mechanism command to enable a specific delay measurement mechanism:
    • delay: enables the delay request-response mechanism, in which information about the clock and time is calculated based on the delay of an entire link between the master and slave clocks. Only the slave clock sends Delay_Req packets to the master clock, and the master clock replies with Delay_Resp packets. Upon receipt, the slave clock uses information carried in Delay_Resp packets to correct time signals.
    • pdelay: enables the peer delay mechanism, in which information about the clock and time is calculated based on the delay time of each link along the path between the master and slave clocks. In this mode, the master and slave clocks can send Pdelay_Rep packets to each other and then correct time signals based on the Pdelay_Resp packets. Upon receipt of the responses, the slave or master clock uses information carried in Delay_Resp packets to correct time signals.

    The PDelay mechanism helps rapidly correct the difference between the delay time in opposite directions on the network, on which the master and slave clocks obtain the delay time in opposite directions.

    • Both ends of a link must use the same delay measurement mechanism.

    • If an E2ETC, an E2ETCOC, a P2PTC, and a P2PTCOC use the default delay measurement mechanism, their interfaces can directly be enabled with 1588v2.

  • Asymmetric delay corrections

    Although the delay time for sending packets differs from that for receiving packets, 1588v2 considers that the opposite paths have the same delay time. To compensate for the difference between the delay time for sending packets and the delay time for receiving packets, run the ptp asymmetry-correction command to set the asymmetry correction value. A 1588v2 device automatically uses the asymmetry correction value in path delay calculation complying with the Pdelay or delay measurement mechanism.

  • Timestamping modes

    1588v2 adds timestamps into packets to record the time when these packets are sent. 1588v2 uses timestamps to adjust clock signals and implement clock synchronization. Either of the following parameters can be specified in the ptp clock-step command to configure a command:
    • one-step: A Sync message in Delay mode and a PDelay_Resp message in PDelay mode are stamped with the time when these messages are sent.
    • two-step: A Sync message in Delay mode and a PDelay_Resp message in PDelay mode only record the time when they are generated, but carry no timestamps. A Follow_Up message is stamped with the time when the Sync message was sent, and a PDelay_Resp_Follow_Up message is stamped with the time when the PDelay_Resp message was sent.

    The NetEngine 8000 F supports the one-step mode by default. The NetEngine 8000 F that uses the one-step mode can identify Follow_Up messages sent by another device that uses the two-step mode.

    1588v2 interfaces that support different timestamping modes can communicate with each other.

Procedure

  • Perform the following steps on each OC:
    1. Run system-view

      The system view is displayed.

    2. Run ptp enable

      1588v2 is enabled on the device.

    3. Run interface interface-type interface-number

      The interface view is displayed.

    4. (Optional) Run ptp delay-mechanism { delay | pdelay }

      A delay measurement mechanism is configured for the router.

      Two interfaces on both ends of a link must use the same delay measurement mechanism. A delay measurement mechanism inconsistency causes a communication failure.

    5. Run ptp enable

      1588v2 is enabled on the interface.

    6. (Optional) Run ptp asymmetry-correction { positive | negative } correction-value

      The asymmetric correction time is set for 1588v2 packets to be sent.

    7. (Optional) Run ptp clock-step { one-step | two-step }

      The timestamping mode is specified for 1588v2 packets.

    8. Run commit

      The configuration is committed.

  • Perform the following steps on each BC:
    1. Run system-view

      The system view is displayed.

    2. Run ptp enable

      1588v2 is enabled on the device.

    3. Run interface interface-type interface-number

      The interface view is displayed.

    4. (Optional) Run ptp delay-mechanism { delay | pdelay }

      A delay measurement mechanism is configured for the router.

      Two interfaces on both ends of a link must use the same delay measurement mechanism. A delay measurement mechanism inconsistency causes a communication failure.

    5. Run ptp enable

      1588v2 is enabled on the interface.

    6. (Optional) Run ptp announce-drop enable

      The BC is configured to discard Announce packets.

      routers exchange Announce packets to establish synchronization relationships. If an interface of a 1588v2 router discards Announce packets, the router cannot receive clock information from other 1588v2 routers. The ptp announce-drop enable command is run on a user-side 1588v2 interface.

    7. (Optional) Run ptp asymmetry-correction { positive | negative } correction-value

      The asymmetric correction time is set for 1588v2 packets to be sent.

    8. (Optional) Run ptp clock-step { one-step | two-step }

      The timestamping mode is specified for 1588v2 packets.

    9. Run commit

      The configuration is committed.

  • Perform the following steps on each TC:
    1. Run system-view

      The system view is displayed.

    2. Run ptp enable

      1588v2 is enabled on the device.

    3. Run interface interface-type interface-number

      The interface view is displayed.

    4. Run ptp asymmetry-correction { positive | negative } correction-value

      The asymmetric correction time is set for 1588v2 packets to be sent.

    5. Run ptp enable

      1588v2 is enabled on the interface.

    6. Run ptp clock-step { one-step | two-step }

      The timestamping mode is specified for 1588v2 packets.

    7. Run commit

      The configuration is committed.

  • Perform the following steps on each TCOC:
    1. Run system-view

      The system view is displayed.

    2. Run ptp enable

      1588v2 is enabled on the device.

    3. Run interface interface-type interface-number

      The interface view is displayed.

    4. Run ptp enable

      1588v2 is enabled on the interface.

    5. Run ptp tcoc-clock-id clock-source-id port-num port-num

      The clock source traced by an interface on the TCOC is configured.

      Unlike a TC, a TCOC has an OC interface to implement frequency synchronization. The TCOC also has TC interfaces to transparently transmit 1588v2 packets.

      To specify a clock source that the OC interface on the TCOC tracks, run the ptp tcoc-clock-id command. The OC interface can then receive 1588v2 packets to synchronize frequencies with the master clock interface. If the ptp tcoc-clock-id command is not run on the OC interface of the TCOC, each TCOC interface functions as a TC interface, which only transparently transmits 1588v2 packets.

    6. Run ptp asymmetry-correction { positive | negative } correction-value

      The asymmetric correction time is set for 1588v2 packets to be sent.

    7. Run ptp clock-step { one-step | two-step }

      The timestamping mode is specified for 1588v2 packets.

    8. Run commit

      The configuration is committed.

  • Perform the following steps on each TCandBC:
    1. Run system-view

      The system view is displayed.

    2. Run ptp enable

      1588v2 is enabled on the device.

    3. Run interface interface-type interface-number

      The interface view is displayed.

    4. Run ptp port-type { bc | tc }

      The clock type of the interface is set to TC or BC.

    5. Run ptp domain domain-value

      A domain ID is set in the interface view of a TC interface.

      A BC interface uses the same domain ID as that configured in the system view. The TC interface on the TCandBC uses another domain ID configured in the interface view.

    6. (Optional) Run ptp delay-mechanism { delay | pdelay }

      A delay measurement mechanism is configured for the router.

      Two interfaces on both ends of a link must use the same delay measurement mechanism. A delay measurement mechanism inconsistency causes a communication failure.

    7. Run ptp enable

      1588v2 is enabled on the interface.

    8. Run ptp enable

      1588v2 is enabled on the device.

    9. (Optional) Run ptp asymmetry-correction { positive | negative } correction-value

      The asymmetric correction time is set for 1588v2 packets to be sent.

    10. (Optional) Run ptp clock-step { one-step | two-step }

      The timestamping mode is specified for 1588v2 packets.

    11. Run commit

      The configuration is committed.

Copyright © Huawei Technologies Co., Ltd.
Copyright © Huawei Technologies Co., Ltd.
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