Configuration Precautions for Physical Layer Clock Synchronization

Feature Requirements

Table 1 Feature requirements

Feature Requirements

Series

Models

When the 2M ring does not trace the source, the output action ("clock bits { bits0 | bits1 | bits2 } lti-action-2mbps { send-dnu | send-ais }") of the BITS port is valid only when the BITS signal type is set to 2mbps.

NetEngine 8000 F

NetEngine 8000 F2A/NetEngine 8000 F1A

In the port extension scenario, the inter-device clock synchronization solution supports only physical-layer clock synchronization and 1588v2 time synchronization.

NetEngine 8000 F

NetEngine 8000 F2A/NetEngine 8000 F1A

O/E converters do not support synchronous Ethernet or PTP time synchronization. The frequency/time synchronization performance cannot be met.

When planning the clock/time topology, do not deploy the clock/time source on an interface with an O/E conversion module. Instead, use an optical module or an electrical interface.

NetEngine 8000 F

NetEngine 8000 F2A/NetEngine 8000 F1A

The clock source with an abnormal frequency offset can participate in clock source selection again only when frequency offset detection is enabled and the frequency offset switching function is enabled.

NetEngine 8000 F

NetEngine 8000 F2A/NetEngine 8000 F1A

Copyright © Huawei Technologies Co., Ltd.
Copyright © Huawei Technologies Co., Ltd.
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