display clock source (all views)

Function

The display clock source command displays clock synchronization configurations and clock source information.

Format

display clock { config | source [ interface { interface-name | interface-type interface-number } ] }

display clock source freq-deviation

display clock source ptp

display clock source bits0

Parameters

Parameter	Description	Value
bits0	Indicates that the external BITS clock source is a BITS0 interface.	-
config	Specifies the configuration.	-
source	Specifies the source.	-
interface interface-name	Specifies the interface name.	-
interface interface-type	Specifies the interface type.	-
interface interface-number	Specifies the interface number.	-
freq-deviation	Displays the frequency deviation values of clock sources. The frequency deviation value is calculated by comparing the frequency of local oscillator and the frequency of the external clock signal.	-
ptp	Specify precision time protocol configuration.	-

Views

All views

Default Level

1: Monitoring level

Task Name and Operations

Task Name	Operations
clksync	read

Usage Guidelines

Usage Scenario

After you complete clock synchronization configurations on the device, run the display clock config command to view the configuration results.

During routine maintenance, you can run the display clock source command to view information about all clock sources, including the traced clock source.

You can run the display clock source freq-deviation command to view the frequency deviation values of clock sources. If the absolute frequency deviation value of a clock source is greater than or equal to 9.2, the frequency deviation detection status is abnormal. If the absolute frequency deviation value is less than 9.2, the frequency deviation detection status is normal.

Example

The actual command output varies according to the device. The command output here is only an example.

# Display information about a specified clock source.

<HUAWEI> display clock source  interface GigabitEthernet 0/1/8
  Pri(sys/2m-1/2m-2) :5  /---/---
  SSM Configure/learning :--/esec
  ClockId Configure/learning :0/0
  State :normal

  SSM code :0x0b
  Enhanced SSM code :0x22
  ClockIdentity :00259e1000013231
  Flag :0x01
  Number of cascaded eSECs :00
  Number of cascaded SECs :01

# Display information about all clock sources, including the traced clock source.

<HUAWEI> display clock source
System trace source State:    lock mode
                              into pull-in range
 Current system trace source: bits0
 Current 2M-1 trace source:   system PLL
 Current 2M-2 trace source:   system PLL
 Frequency lock success:      yes

 Master board
 Source        Pri(sys/2m-1/2m-2)   In-SSM     Out-SSM    State      Ref
 --------------------------------------------------------------------------
 bits0           1/---/---         sec        dnu       normal     yes
 GE0/1/0         2/---/---         sec        sec       normal     yes
 GE0/1/8         3/---/---         sec        sec       normal     yes

# Display clock synchronization configurations.

<HUAWEI> display clock config
clock freq deviation detect :enable                                                                                                
  clock unk map             :dnu                                                                                                   
  system pll run mode       :normal                                                                                                
  bits output threshold     :dnu
  source input threshold    :sec                                                                                                   
  tod protocol              :ubx                                                                                                   
                                                                                                                                    
  switch config                                                                                                                     
    sys pll                 :auto mode                                                                                              
    2msync-1 pll            :auto mode                                                                                              
    2msync-2 pll            :auto mode                                                                                              
    SSM control             :off                                                                                                    
    Extend SSM control      :off                                                                                                    
    Enhanced SSM control    :off                                                                                                    
    internal clockid        :0                                                                                                      
    switch mode             :revertive                                                                                              
    wtr                     :0min                                                                                                   
    holdoff time            :1000ms                                                                                                 
                                                                                                                                    
  source config                                                                                                                     
  bits0                                                                                          
    Sync disable                                                                                                                    
    Sa-bit                  :sa4                                                                                                       
    Signal-type             :2mbps                                                                                                     
  bits1                                                                                                                             
    Sync disable                                                                                                                    
    Sa-bit                  :sa4                                                                                                       
    Signal-type             :2mbps                                                                                                     
  bits2                                                                                                                             
    Sync disable                                                                                                                    
    Sa-bit                  :sa4                                                                                                       
    Signal-type             :2mbps                                                                                                     
  GigabitEthernet0/1/1                                                                                                             
    Sync disable                                                                                                                    
    Pri(sys/2m-1/2m-2)      :1/--/--                                                                                                
    Esmc send disable
  GigabitEthernet0/1/2                                                                                                             
    Sync disable                                                                                                                    
    Pri(sys/2m-1/2m-2)      :1/--/--                                                                                                
  GigabitEthernet0/1/3                                                                                                             
    Sync enable                                                                                                                     
    Pri(sys/2m-1/2m-2)      :1/--/--                                                                                                
  GigabitEthernet0/1/4                                                                                                            
    Sync disable                                                                                                                    
    Pri(sys/2m-1/2m-2)      :1/--/--                                                                                                
    Bundle                  :1
  GigabitEthernet0/1/5                                                                                                            
    Sync disable                                                                                                                    
    Pri(sys/2m-1/2m-2)      :1/--/--                                                                                                
    Bundle                  :1
  ptp                                                                                                                               
    Sync enable                                                                                                                     
    Pri(sys)                :1

# Display the frequency deviation values of clock sources.

<HUAWEI> display clock source freq-deviation
  Frequency deviation detect:       enable
  Source                               Freq-deviation-value
  ----------------------------------------------------------
  * bits0                             0.26ppm(normal)
    bits0                             ---    
    GE0/1/0                           0.31ppm(normal)
    GE0/1/8                             ---

**Table 1** Description of the **display clock source (all views)** command output
Item	Description
clock freq deviation detect	Whether frequency deviation detection is enabled for clock signals: enable: Frequency deviation detection is enabled for clock signals. disable: Frequency deviation detection is disabled for clock signals.
clock unk map	Mapping level of the clock source with an SSM level of unk.
source input threshold	output SSM threshold of the clock source. eprtc. prtc. eprc. prc. ssua. ssub. esec. sec. dnu.
source config	Clock source configuration.
Pri(sys/2m-1/2m-2)	Priority of the clock source: sys: priority of the clock source that participates in system clock source selection. 2m-1: priority of the clock source that participates in 2M PLL-1 clock source selection. 2m-2: priority of the clock source that participates in 2M PLL-2 clock source selection.
SSM control	Whether SSM levels are configured to participate in clock source selection: on: SSM levels participate in clock source selection. off: SSM levels do not participate in clock source selection.
SSM Configure/learning	Input SSM quality level of a port: -configure: specifies the configured input SSM quality level. -learning: indicates the learned input SSM quality level.
SSM code	Standard SSM value learned by the port.
ClockId Configure/learning	ID of the extended SSM input clock source: -configure: ID of the configured input clock source. -learning: ID of the learned input clock source.
State	Status of the clock source: initial: The clock source works in the off-line state. normal: The clock source works in the normal state. normal*: The clock source is not involved in the frequency deviation detection. abnormal: The clock source works in the abnormal state. abnormal(phy): The electrical port is negotiated as in the master state (A port in the master state cannot participate in clock source selection but can be used as a clock source port to synchronize clock information with downstream devices). abnormal(ssm): The clock source works in the abnormal state in receiving ssm packets. abnormal(freq): The clock source works in the abnormal state in the frequency deviation detection. holdoff: The clock source works in the holdoff state. wtr: The clock source works in the WTR state.
Enhanced SSM control	Whether Enhanced SSM function is enabled: on: Enhanced SSM function is enabled. off: Enhanced SSM function is disabled.
Enhanced SSM code	Enhanced SSM value learned by the port.
ClockIdentity	Indicates the ID of the enhanced SSM clock source.
Flag	Bit 0 means mixed SEC/eSEC (i.e., 1 if at least one of the clocks is not an eSEC; 0 if all clocks are eSEC); bit 1 means partial chain (i.e., 1, if the TLV has been generated in the middle of the chain and the count of the SEC/eSEC is incomplete); bits 2-7 reserved for future use.
Number of cascaded eSECs	Number of cascaded eSECs.
Number of cascaded SECs	Number Of SECs.
System trace source State	Status of the system clock: lock mode: The system clock works in lock mode. freerun mode: The system clock works in free-running mode. hold mode: The system clock works in hold mode.
Current system trace source	Clock source for the system clock.
Current 2M-1 trace source	Clock source for the 2M PLL-1 clock.
Current 2M-2 trace source	Clock source for the 2M PLL-2 clock.
system pll run mode	Status of the system PLL.
Frequency lock success	Whether frequency locking succeeds: yes: Frequency locking succeeds. no: Frequency locking fails.
Frequency deviation detect	Frequency deviation detect.
Master board	Master clock board.
Source	Name of the clock source.
In-SSM	SSM level received by clock signals or configured SSM level.
Out-SSM	Output SSM level of clock signals.
Ref	Indicates whether this clock source participates in clock source selecting. Yes: Indicates this clock source participates in clock source selecting. No: Indicates this clock source does not participate in clock source selecting.
bits output threshold	Lowest output threshold of the external clock source.
tod protocol	Protocol type that the packets carrying TOD information abide by.
switch config	Clock selection configuration.
switch mode	Clock reversion mode: revertive: revertive mode. non-revertive: non-revertive mode.
sys pll	System PLL.
2msync-1 pll	2msync-1 PLL.
2msync-2 pll	2msync-2 PLL.
Extend SSM control	Whether Extend SSM function is enabled: on: Extend SSM function is enabled. off: Extend SSM function is disabled.
internal clockid	Clock ID of the internal clock source.
wtr	WTR time for a status change after a clock source is restored.
holdoff time	Indicates the holdoff time after clock source signals are lost.
Sync enable	Status of clock synchronization for the BITS clock source: Sync enable: clock synchronization is enabled. Sync disable: clock synchronization is disabled.
Sa-bit	Sa timeslot carrying the SSM level.
Signal-type	Type of the clock signal.
Bundle	Bundle group ID of the clock source.
Freq-deviation-value	Frequency deviation value. The format is Symbol (only negative signs are displayed)+Frequency deviation value+Unit (ppm)+Frequency deviation detection status (abnormal or normal). If "---" is displayed, the frequency deviation value of the clock source cannot be detected.