Configuring a Clock Source

Context

Before configuring clock synchronization on the NetEngine 8000 F, configure a clock source. The NetEngine 8000 F supports building integrated timing supply (BITS), Precision Time Protocol (PTP), and line clock sources. Perform one of the following configurations based on the clock source used on a clock synchronization network:

The actual number of BITS interfaces varies with the hardware configuration. You need to set them based on the actual situation. Similar details are omitted in the following.

Procedure

  • Configure a BITS clock source.
    1. Run system-view

      The system view is displayed.

    2. Run clock bits-type bits0 { 2mhz | 2mbps }

      A signal type is configured for the BITS clock source.

    3. Run clock source bits0 synchronization enable

      Clock synchronization is enabled for the BITS clock source.

    4. Run clock source bits0 priority priority-value

      A priority is configured for the BITS clock source. A smaller value indicates a higher priority.

    5. (Optional) Run clock sa-bit { sa4 | sa5 | sa6 | sa7 | sa8 } source bits0

      The timeslot from which the BITS clock source extracts SSM level information is configured.

    6. (Optional) Run clock source bits0 ssm { prc | ssua | ssub | sec | dnu | unk | prtc | eprtc | esec | eprc }

      The SSM level of the BITS clock source is configured.

      If the signal type of the BITS clock source is 2mhz, the BITS clock source cannot directly extract SSM level information from clock signals. If you have configured SSM levels to participate in clock source selection, run this command to manually configure an SSM level for the clock source.

    7. (Optional) Run clock source bits0 clock-id clockid-value

      The clock ID of the BITS clock source is configured.

      If you have enabled the extended SSM function, configure a clock ID for the BITS clock source.

    8. (Optional) Run clock bits output-threshold { prc | ssua | ssub | sec | dnu }

      A threshold is configured for the SSM level of clock signals sent by the external clock source.

      If the SSM level of clock signals sent by the BITS clock source is lower than the configured threshold, the BITS clock source stops sending clock signals.

    9. Run commit

      The configuration is committed.

  • Configure a PTP clock source.
    1. Run system-view

      The system view is displayed.

    2. Run ptp device-type { oc | bc | e2etc | p2ptc | e2etcoc | p2ptcoc | tcandbc }

      The clock mode for a 1588v2 device is configured.

    3. Run ptp enable

      PTP is enabled.

    4. Run interface interface-type interface-number

      The interface view is displayed.

    5. Run ptp enable

      PTP is enabled on a specific interface.

    6. Run quit

      Return to the system view.

    7. Run clock source ptp priority priority-value

      A priority is configured for the PTP clock source.

      A smaller value indicates a higher priority.

    8. Run clock source ptp synchronization enable

      Clock synchronization is enabled for the PTP clock source.

    9. (Optional) Run clock source ptp ssm { dnu | prc | sec | ssua | ssub | unk | prtc | eprtc | esec | eprc }

      An SSM level is configured for the PTP clock source.

      If you have configured SSM levels to participate in clock source selection, run this command to manually configure an SSM level for the PTP clock source.

    10. (Optional) Run clock source ptp clock-id clockid-value

      A clock ID is configured for the PTP clock source.

    11. Run commit

      The configuration is committed.

  • Configure a line clock source.
    1. Run system-view

      The system view is displayed.

    2. Run interface interface-type interface-number

      The interface view is displayed.

    3. Run clock synchronization enable

      Clock synchronization is enabled for the line clock source.

    4. (Optional) Run clock [ 2msync-1 ] priority priority-value

      A priority is configured for the line clock source.

      A smaller value indicates a higher priority.

    5. (Optional) Run clock ssm { dnu | prc | sec | ssua | ssub | unk | prtc | eprtc | esec | eprc }

      An SSM level is configured for the line clock source.

    6. (Optional) Run clock clock-id clockid-value

      A clock ID is configured for the line clock source.

    7. (Optional) To prevent a clock loop when two or more clock links exist between two devices, run clock bundle bundle-value

      A bundle group ID is configured for the line clock source, and the line clock source is added to a bundle group.

    8. Run commit

      The configuration is committed.

Copyright © Huawei Technologies Co., Ltd.
Copyright © Huawei Technologies Co., Ltd.
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