Example for Configuring Clock Synchronization on a Ring Network

Networking Requirements

Figure 1 shows a ring network. On this network, Device A and Device C connect to one external building integrated timing supply system (BITS) each. During network deployment, each device automatically selects a clock source based on the clock signals transmitted from DeviceA and DeviceC.

Figure 1 Networking diagram of configuring clock synchronization on a ring network

The configurations in this example are performed on Device A, Device B, Device C, and Device D. HUAWEI NetEngine 8000 F Series can function as Device A, Device B, Device C, and Device D.

Interfaces 1 and 2 in this example are GE 0/1/0, GE 0/1/8, respectively.



Precautions

None

Configuration Roadmap

The configuration roadmap is as follows:

  1. Configure a clock synchronization mode and enable the devices to select clock sources based on SSM levels.
  2. Configure clock sources.
  3. Disable Device A from tracing clock signals from its connected BITS and check whether devices go to trace clock signals from the BITS connected to Device C.

Data Preparation

To complete the configuration, plan each router's clock source priority and SSM level, as listed in Table 1.

Table 1 Clock source priority and SSM level of each router

router

Clock Source in Use

Priority

DeviceA

BITS0

1

GE0/1/0

2

GE0/1/8

-

DeviceB

GE0/1/0

1

GE0/1/8

2

DeviceC

BITS0

1

GE0/1/0

-

GE0/1/8

3

DeviceD

GE0/1/0

1

GE0/1/8

2

Procedure

  1. Enable the devices to select clock sources based on SSM levels.

    # Configure Device A.

    <HUAWEI> system-view
    [~HUAWEI] sysname DeviceA
    [*HUAWEI] commit
    [~DeviceA] clock ssm-control on
    [*DeviceA] commit

    # Configure other devices by using the same method for configuring Device A.

  2. Configure clock sources.

    # Configure Device A.

    [*DeviceA] clock bits-type bits0 2mbps
    [*DeviceA] clock source bits0 synchronization enable
    [*DeviceA] clock source bits0 priority 1
    [*DeviceA] commit
    [~DeviceA] quit
    [~DeviceA] interface gigabitethernet 0/1/0
    [~DeviceA-GigabitEthernet0/1/0] clock synchronization enable
    [*DeviceA-GigabitEthernet0/1/0] clock priority 2
    [*DeviceA-GigabitEthernet0/1/0] commit
    [~DeviceA-GigabitEthernet0/1/0] quit
    [~DeviceA] interface gigabitethernet 0/1/8
    [*DeviceA-GigabitEthernet0/1/8] clock synchronization enable
    [*DeviceA-GigabitEthernet0/1/8] commit

    # Configure Device B.

    [~DeviceB] interface gigabitethernet 0/1/0
    [~DeviceB-GigabitEthernet0/1/0] clock synchronization enable
    [*DeviceB-GigabitEthernet0/1/0] clock priority 1
    [*DeviceB-GigabitEthernet0/1/0] commit
    [~DeviceB-GigabitEthernet0/1/0] quit
    [~DeviceB] interface gigabitethernet 0/1/8
    [*DeviceB-GigabitEthernet0/1/8] clock synchronization enable
    [*DeviceB-GigabitEthernet0/1/8] clock priority 2
    [*DeviceB-GigabitEthernet0/1/8] commit

    # Configure Device D by using the same method for configuring Device B.

    # Configure Device C.

    [*DeviceC] clock bits-type bits0 2mbps
    [*DeviceC] clock source bits0 synchronization enable
    [*DeviceC] clock source bits0 priority 1
    [*DeviceC] commit
    [~DeviceC] quit
    [~DeviceC] interface gigabitethernet 0/1/0
    [*DeviceC-GigabitEthernet0/1/0] clock synchronization enable
    [*DeviceC-GigabitEthernet0/1/0] commit
    [~DeviceC-GigabitEthernet0/1/0] quit
    [~DeviceC] interface gigabitethernet 0/1/8
    [*DeviceC-GigabitEthernet0/1/8] clock synchronization enable
    [*DeviceC-GigabitEthernet0/1/8] clock priority 3
    [*DeviceC-GigabitEthernet0/1/8] commit

  3. Verify the configuration.

    Run the display clock source command on Device A, Device B, Device C, and Device D to check the clock synchronization configurations and clock source information.

    # Check the clock synchronization configurations and clock source information on Device A.

    <HUAWEI> display clock source
    System trace source State:    lock mode
                                  into pull-in range
     Current system trace source: bits0
     Current 2M-1 trace source:   system PLL
     Frequency lock success:      yes
    
     Master board
     Source        Pri(sys/2m-1)   In-SSM     Out-SSM    State      Ref-Source
     --------------------------------------------------------------------------
     bits0            1/---         ssua        --        normal     yes
     GE0/1/0            2/---         dnu        ssua       normal     yes
     GE0/1/8            ---/---         ssua        ssua       normal     yes
     

    # Check the clock synchronization configurations and clock source information on DeviceB.

    <HUAWEI> display clock source
    System trace source State:    lock mode
                                  into pull-in range
     Current system trace source: GigabitEthernet0/1/0
     Current 2M-1 trace source:   system PLL
     Frequency lock success:      yes
    
     Master board
     Source        Pri(sys/2m-1)   In-SSM     Out-SSM    State      Ref-Source
     --------------------------------------------------------------------------
     GE0/1/0          1/---         ssua        dnu       normal     yes
     GE0/1/8          2/---         dnu        ssua       normal     yes
     

    # Check the clock synchronization configurations and clock source information on DeviceC.

    <HUAWEI> display clock source
    System trace source State:    lock mode
                                  into pull-in range
     Current system trace source: GigabitEthernet0/1/8
     Current 2M-1 trace source:   system PLL
     Frequency lock success:      yes
    
     Master board
     Source        Pri(sys/2m-1)   In-SSM     Out-SSM    State      Ref-Source
     --------------------------------------------------------------------------
     bits0            1/---         ssub        --       normal     yes
     GE0/1/0          ---/---       dnu        ssua       normal     yes
     GE0/1/8          3/---        ssua        dnu       normal     yes
     

    # Check the clock synchronization configurations and clock source information on DeviceD.

    <HUAWEI> display clock source
    System trace source State:    lock mode
                                  into pull-in range
     Current system trace source: GigabitEthernet0/1/0
     Current 2M-1 trace source:   system PLL
     Frequency lock success:      yes
    
     Master board
     Source        Pri(sys/2m-1)   In-SSM     Out-SSM    State      Ref-Source
     --------------------------------------------------------------------------
     GE0/1/0          1/---         ssua        dnu       normal     yes
     GE0/1/8          2/---         ssua        ssua       normal     yes

Configuration Files

  • Configuration file of Device A

    #
     sysname DeviceA
    #
    clock ssm-control on
    clock bits-type bits0 2mbps 
    clock source bits0 synchronization enable 
    clock source bits0 priority 1 
    #
    interface GigabitEthernet0/1/0
     clock synchronization enable
     clock priority 2
    #
    interface GigabitEthernet0/1/8
     clock synchronization enable
    #
    return 
  • Configuration file of Device B

    #
     sysname DeviceB
    #
    clock ssm-control on
    #
    interface GigabitEthernet0/1/0
     clock synchronization enable
     clock priority 1
    #
    interface GigabitEthernet0/1/8
    clock synchronization enable
    clock priority 2
    #
    return 
  • Configuration file of Device C

    #
     sysname DeviceC
    #
    clock ssm-control on
    clock bits-type bits0 2mbps 
    clock source bits0 synchronization enable 
    clock source bits0 priority 1 
    #
    interface GigabitEthernet0/1/0
     clock synchronization enable
    #
    interface GigabitEthernet0/1/8
     clock synchronization enable
     clock priority 3
    #
    return 
  • Configuration file of Device D

    #
     sysname DeviceD
    #
    clock ssm-control on
    #
    interface GigabitEthernet0/1/0
     clock synchronization enable
     clock priority 1
    #
    interface GigabitEthernet0/1/8
     clock synchronization enable
     clock priority 2
    #
    return 
Copyright © Huawei Technologies Co., Ltd.
Copyright © Huawei Technologies Co., Ltd.
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