Clock Source Selection

After the device receives multiple clock signals and sends them to the clock chip, the clock chip needs to select the most precise clock source as the system clock according to certain clock source selection rules to provide clock signals for each interface of the device.

Clock Sources

A device that provides clock signals for another device is called a clock source. The following clock sources are listed in descending order of accuracy:

External clock source

A device is connected to an external clock of a higher level through its Ethernet interfaces.
PTP clock source

A device extracts clock signals from 1588v2 messages using 1588v2.
Line clock source

A device extracts clock signals from the Ethernet line bit stream through Ethernet interfaces. This mode is synchronous Ethernet.
Internal clock source

A device uses its reference clock (for example, the clock provided by the clock chip) as the working clock of its interfaces.

The switch does not support the external clock source.

Factors in Selecting Clock Sources

When multiple clock sources are available, a switch selects a clock source as its reference clock according to the clock source priority and Synchronization Status Message (SSM) quality level.

Clock source priority

The default priority for a clock source is 0, indicating that this clock source does not participate in clock source selection. To enable the clock source to participate in clock source selection, specify a priority for it.

A lower priority value indicates a higher priority of a clock source.
Clock source SSM quality level

An SSM is a group of codes used to indicate the clock quality level on a synchronized network. SSM reflects the level of synchronous timing signals transmitted on a synchronous timing link. A higher clock accuracy indicates a higher SSM quality level. A device can be configured to select a clock source according to the SSM quality level.

SSM quality levels are sorted in descending order of preference: primary reference clock (PRC), Synchronization Supply Unit A (SSU-A), Synchronization Supply Unit B (SSU-B), SDH equipment clock (SEC), and Do Not Use (DNU).

Clock Source Selection Modes

When multiple clock sources are available, a switch can select the optimal clock source in automatic, manual, or forcible mode:

Automatic mode: The system uses the automatic clock source selection algorithm to determine the clock source to be traced based on the priorities and SSM quality levels of clock sources.
When multiple clock sources are available on the network, a switch selects a clock source according to the following rules:
1. If no SSM quality level is specified for clock source selection, the switch selects the clock source to be traced based on the priorities configured for the clock sources.
2. If an SSM quality level is specified for clock source selection:
  1. The switch selects the clock source to be traced based on the SSM quality levels of clock sources.
  2. If there are multiple clock sources with the same SSM quality level, the switch selects the clock source to be traced based on the priorities of these clock sources.
Manual mode: The clock source to be traced is manually specified using commands, and this clock source must have the highest SSM quality level.
Forcible mode: The clock source to be traced is forcibly specified using commands, which can be any clock source.

Protection switching can help mitigate the effects of clock source failures. For details about using protection switching with different clock source selection modes, see Protection Switching.

Using the automatic mode is recommended. In this mode, a switch can dynamically select the optimal clock source to be traced based on the SSM quality level.

Clock Chip Working States

After the switch selects a clock source, it constantly synchronizes clock signals from the clock source. During clock source selection and clock signal tracing, the clock chip has three states:

Lock
If the switch selects a clock source, the frequency of the clock needs to be traced and locked, which is implemented through the PPL. The clock source may be the master clock or may use the clock signals delivered by the built-in clock source of the upper-level NE.
Hold
When tracing a clock source, the clock chip keeps storing data. When the clock source cannot be used, the clock chip maintains the frequency characteristics of this clock source according to the clock data saved previously to provide the same clock signals as the previous master clock. The switch can be configured to work in hold state by using the clock run-mode hold slot slot-id command.
Free
When there is no clock source to be traced, the internal oscillator of the clock works in free state. In this case, the clock chip uses the clock generated by the oscillator as the external clock. The switch can be configured to work in free state by using the clock run-mode free slot slot-id command.