CLKM_1.3.6.1.4.1.2011.5.25.186.1.8.6 hwClockSourceOutputBelowThreshold

Trap Buffer Description

The SSM of output below threshold notification. (hwClockAttributeChassisIndex=[hwClockAttributeChassisIndex], hwClockChassisId=[hwClockChassisId], hwClockPllId=[hwClockPllId], hwClockAttributeOutThreshold=[hwClockAttributeOutThreshold], hwClockAttributeOutValue=[hwClockAttributeOutValue], hwClockCurSourceName=[hwClockCurSourceName])

The SSM level of output clock signals was below the lower limit.

In VS mode, this trap is supported only by the admin VS.

Trap Attributes

Trap Attribute	Description
Alarm or Event	Alarm
Trap Severity	Warning
Mnemonic Code	hwClockSourceOutputBelowThreshold
Trap OID	1.3.6.1.4.1.2011.5.25.186.1.8.6
MIB	HUAWEI-CLOCK-MIB
Alarm ID	0x09af0004
Alarm Name	hwClockSourceOutputBelowThreshold
Alarm Type	equipmentAlarm
Raise or Clear	Raise
Match trap	CLKM_1.3.6.1.4.1.2011.5.25.186.1.8.14 hwClockSourceOutputBelowThresholdResume

Trap Buffer Parameters

Parameter	Description
hwClockAttributeChassisIndex	Indicates the index of the chassis where the non-PTP clock source is located. In the case of a single chassis, the index is 1. For a chassis where a PTP clock source is located, the index is invalid.
hwClockChassisId	Chassis id of the clock source.
hwClockPllId	Id of the clock source type. values: System(1), system PLL. sync2M-1(2), 2M PLL-1. sync2M-2(3), 2M PLL-2.
hwClockAttributeOutThreshold	Threshold of the external Clock output. values: prc(2). ssua(4). ssub(8). sec(11). dnu(15). The default value is dnu,and that can config as prc,sec,ssua,ssub.
hwClockAttributeOutValue	SSM of the external Clock output. values: prc(2). ssua(4). ssub(8). sec(11). dnu(15).
hwClockCurSourceName	Name of the current clock source.

VB Parameters

VB OID	VB Name	VB Index
1.3.6.1.4.1.2011.5.25.186.1.7.4	hwClockChassisId	-
1.3.6.1.4.1.2011.5.25.186.1.7.6	hwClockPllId	-
1.3.6.1.4.1.2011.5.25.186.1.9.1.8	hwClockAttributeOutThreshold	hwClockAttributeChassisIndex
1.3.6.1.4.1.2011.5.25.186.1.7.7	hwClockAttributeOutValue	-
1.3.6.1.4.1.2011.5.25.186.1.7.2	hwClockCurSourceName	-

Impact on the System

The output of the PLL will be blocked.

Possible Causes

Cause1: The lower limit to the SSM level of output clock signals was set too high.

Cause2: The SSM level of the signal output by the traced clock source changed.

Procedure

1. Run the display clock config command to check the output threshold of the clock source.

If the output threshold is dnu, no output threshold is set. Then, go to Step 4.
If the output threshold is not dnu, go to Step 2.

2. Run the display clock source command to check the output SSM level of the clock source.

If the output SSM level is lower than the threshold, go to Step 3.
If the output SSM level is not lower than the threshold, go to Step 4.

3. Run the clock bits output-threshold command to set a proper threshold.

4. Collect trap, log, and configuration information, and contact Huawei technical support personnel.

5. End.