CLKM/4/hwClockSourceOutputBelowThreshold_active: The SSM of output below threshold notification. (hwClockAttributeChassisIndex=[hwClockAttributeChassisIndex], hwClockChassisId=[hwClockChassisId], hwClockPllId=[hwClockPllId], hwClockAttributeOutThreshold=[hwClockAttributeOutThreshold], hwClockAttributeOutValue=[hwClockAttributeOutValue], hwClockCurSourceName=[hwClockCurSourceName])
In VS mode, this log is supported only by the admin VS.
| Parameter Name | Parameter Meaning |
|---|---|
|
hwClockAttributeChassisIndex |
Indicates the index of the chassis where the non-PTP clock source is located. In the case of a single chassis, the index is 1. For a chassis where a PTP clock source is located, the index is invalid. |
|
hwClockChassisId |
Chassis id of the clock source. |
|
hwClockPllId |
Id of the clock source type. values: System(1), system PLL. sync2M-1(2), 2M PLL-1. sync2M-2(3), 2M PLL-2. |
|
hwClockAttributeOutThreshold |
Threshold of the external Clock output. values: prc(2). ssua(4). ssub(8). sec(11). dnu(15). The default value is dnu,and that can config as prc,sec,ssua,ssub. |
|
hwClockAttributeOutValue |
SSM of the external Clock output. values: prc(2). ssua(4). ssub(8). sec(11). dnu(15). |
|
hwClockCurSourceName |
Name of the current clock source. |
Cause1: The lower limit to the SSM level of output clock signals was set too high.
Cause2: The SSM level of the signal output by the traced clock source changed.
1. Run the display clock config command to check the output threshold of the clock source.
2. Run the display clock source command to check the output SSM level of the clock source.
3. Run the clock bits output-threshold command to set a proper threshold.
4. Collect trap, log, and configuration information, and contact Huawei technical support personnel.
5. End.